Data receivers often receive distorted signals, particularly in long distance transmission systems at high bit rates, for instance over standard signal fibre cables. Here, inter-symbol interference (ISI), chromatic dispersion (CD), polarisation mode dispersion (PMD), transmitter chirp, extinction ratio, fibre non-linearity may occur and result in the so-called reduced eye opening. The incoming data at the receiver can be considered as a varying analogue signal from which a timing or clock information can be recovered which is necessary to sample the incoming signal at appropriate intervals to recover the data. This function is commonly accomplished with the aid of a phase locked loop (PLL) which includes a phase detector (PD), a loop filter (LF) and a voltage controlled oscillator (VCO). A well-known phase detector is the early-late phase detector described by Alexander. This detector generates output signals which indicate the direction of the phase deviation relative to a correct timing. These output signals are termed “up” and “down” control signals. The incoming signal which carries the data flow has logical signal values which generally are termed 1 or 0. Between adjacent logical signal values a signal transition may happen. The Alexander phase detector samples two adjacent logical signal values and the signal transition therebetween, these sampled signals being termed “a sample group” in this application. If the sample values which may be 1 or 0 are different among adjacent logical signal values, sampling the signal transition between these adjacent logical signal values may result in a 1 or 0. If the first logical signal value of a group and the signal transition value are equal and differ from the value of the second logical signal value, the clock is too early, and if the signal transition value and the second logical signal value are equal, the clock is too late. In the first case the clock is to slow down and in the second case to speed up. The output signal of the phase detector is converted by the loop filter and fed to the voltage controlled oscillator for controlling the output clock frequency thereof. The clock is fed back to the phase detector and determine the sampling intervals by the position of the rising (or falling)edges of the clock frequency signal. Statistically up and down control signals will happen equally so that the sampling phase controlled by the clock frequency will be correctly adapted to the incoming signal carrying the data flow.
If there are large signal distortions in the incoming data flow, it becomes difficult to correct the phase of the clock in the data receiver, since the performance of the early-late phase detector is degraded and the phase locked loop fails to lock. This is true especially for partial response channels, where differential group delay occurs approximately at the bit transition, the phase detector does not succeed in finding a stable sampling clock phase.